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A unified approach for SoC testing using test data compression and TAM optimization

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4 Author(s)
Iyengar, V. ; IBM Microeletronics, Essex Junction, VT, USA ; Chandra, A. ; Schweizer, S. ; Chakrabarty, K.

We integrate for the first time test access mechanism (TAM) optimization and test data compression into a single test methodology. We show how an integrated test architecture based on TAMs and test data decoders can be designed The proposed approach offers considerable savings in test data volume and testing time. Two case studies using the integrated test architecture are presented.

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Design, Automation and Test in Europe Conference and Exhibition, 2003

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