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Test generation for acyclic sequential circuits with single stuck-at fault combinational ATPG

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2 Author(s)
H. Ichihara ; Fac. of Inf. Sci., Hiroshima City Univ., Japan ; T. Inoue

An existing test generation method with a time-expansion model can achieve high fault efficiency for acyclic sequential circuits. While this model is a combinational circuit, a single stuck-at fault in the original circuit is represented by a multiple one in this model. This paper proposes a test generation method for acyclic sequential circuits with a circuit model, called MS-model, which can express multiple stuck-at faults in a time-expansion model as single stuck-at faults. Our procedure can generate test sequences for acyclic sequential circuits with just a combinational test pattern generation algorithm for single stuck-at faults.

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Design, Automation and Test in Europe Conference and Exhibition, 2003

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