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Selectively clocked CMOS logic style for low-power noise-immune operations in scaled technologies

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2 Author(s)
Naran Sirisantana ; Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA ; Roy, K.

This paper proposes a selectively clocked logic (SCL) style, based on skewed logic, for noise-tolerant low-power high-performance applications. Variations of the logic style, with multiple threshold voltage (MVth-SCL) and multiple oxide thickness (Mtox-SCL) techniques, are also studied. Simulation results indicate that SCL, MVth-SCL, and Mtox-SCL circuits reduce the total power consumption (leakage plus switching power) of the ISCAS benchmark circuits by 51.5%, 53.1%, and 69.6%, respectively, with over 25% improvement in noise immunity compared to Domino circuits with comparable performance.

Published in:

Design, Automation and Test in Europe Conference and Exhibition, 2003

Date of Conference:

2003