Selectively clocked CMOS logic style for low-power noise-immune operations in scaled technologies

This paper proposes a selectively clocked logic (SCL) style, based on skewed logic, for noise-tolerant low-power high-performance applications. Variations of the logic style, with multiple threshold voltage (MV/sub th/-SCL) and multiple oxide thickness (Mt/sub ox/-SCL) techniques, are also studied. Simulation results indicate that SCL, MV/sub th/-SCL, and Mt/sub ox/-SCL circuits reduce the total power consumption (leakage plus switching power) of the ISCAS benchmark circuits by 51.5%, 53.1%, and 69.6%, respectively, with over 25% improvement in noise immunity compared to Domino circuits with comparable performance.