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Background data organisation for the low-power implementation in real-time of a digital audio broadcast receiver on a SIMD processor

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6 Author(s)

In this work we illustrates the strong interaction between the data organisation in background memory and the data format required for sub-word level acceleration. The impact of such interaction is demonstrated on the implementation of a Digital Audio Broadcast Channel Decoder on a TriMedia processor where data format transformations applied on the background memory data enable a substantially better exploitation of the available Single Instruction Multiple Data instructions. As a result, a factor two reduction for both execution time and data memory energy is achieved.

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Design, Automation and Test in Europe Conference and Exhibition, 2003

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