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Enhancing speedup in network processing applications by exploiting instruction reuse with flow aggregation

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3 Author(s)
G. Surendra ; CAD Lab., Indian Inst. of Sci., Bangalore, India ; S. Banerjee ; S. K. Nandy

Instruction reuse is a microarchitectural technique that improves the execution time of a program by removing redundant computations at run-time. Although this is the job of an optimizing compiler they do not succeed many a time due to limited knowledge of run-time data. In this paper, we examine the instruction reuse of an integer ALU and load instructions in network processing applications. Specifically, this paper attempts to answer the following questions: (1) how much instruction reuse is inherent in network processing applications?; (2) can reuse be improved by reducing interference in the reuse buffer?; (3) what characteristics of network applications can be exploited to improve reuse?; and (4) what is the effect of reuse on resource contention and memory accesses? We propose an aggregation scheme that combines the high-level concept of network traffic, i.e. "flows", with a low level microarchitectural feature of programs, i.e. repetition of instructions and data, along with an architecture that exploits temporal locality in incoming packet data to improve reuse. We find that for the benchmarks considered, 1% to 50% of instructions are reused while the speedup achieved varies between 1% and 24%. As a side effect, instruction reuse reduces memory traffic and can therefore be considered as a scheme for low power.

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Design, Automation and Test in Europe Conference and Exhibition, 2003

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