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Optimizing stresses for testing DRAM cell defects using electrical simulation

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4 Author(s)
Z. Al-Ars ; Fac. of Inf. Technol. & Syst., Delft Univ. of Technol., Netherlands ; A. J. van de Goor ; J. Braun ; D. Richter

Stresses are considered an integral part of any modern industrial DRAM test. This paper describes a novel method to optimize stresses for memory testing, using defect injection and electrical simulation. The new method shows how each stress should be applied to achieve a higher fault coverage of a given rest, based on an understanding of the internal behavior of the memory. In addition, results of a fault analysis study, performed to verify the new optimization method, show its effectiveness.

Published in:

Design, Automation and Test in Europe Conference and Exhibition, 2003

Date of Conference:

2003