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The gap between the advances and the utilization of deep submicron (DSM) technology is increasing as the new generation of technology is introduced faster than ever. Signal integrity is one of the most important issues in overcoming this gap. With the increasing coupling capacitance between the high aspect ratio wires, the delay uncertainty is unpredictable in the current design flow. We present an algorithm to generate a global wire bus configuration with minimum delay uncertainty under timing constraints. The timing window information from the timing budget (or specified in IPs) is integrated with modern accurate crosstalk noise models in the proposed algorithm. HSPICE simulations show that the algorithm is very effective and efficient when compared to the buffer insertion scheme with minimum delay. The standard deviation of the delay obtained from the Monte-Carlo simulation is improved by up to 73%. This global wire bus configuration can be adopted in early wire planning to improve the timing closure problem and increase the accuracy of the timing budget.