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Circuit and platform design challenges in technologies beyond 90nm

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3 Author(s)
B. Grundmann ; Dept. of Design Technol., Intel Corp., Hillsboro, OR, USA ; R. Galivanche ; S. Kundu

There are already a huge number of problems for silicon designers and it is likely to just get worse. Many of these problems are technical, associated with shrinking geometries and increasing architecture complexities, but there are a significant number that seem to be caused by procedurally related mistakes and issues. Many of the technical problems are solved and re-solved on a piecemeal basis, focusing on local optimizations of small design-space problems. Unfortunately, many of these local solutions really create a less apparent but larger inefficiency in the whole design flow. The reason for this is that few ever look at the whole design methodology, especially as it applies to large design teams. As a consequence, this lack of oversight for the whole methodology is causing project procedural problems and inefficiencies.

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Design, Automation and Test in Europe Conference and Exhibition, 2003

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