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For many years, CMOS-process scaling has allowed a steady increase in the operating frequency and integration density of integrated circuits. Only recently, however, have we reached a point where it takes several clock cycles for global signals to traverse a complex digital system such as a modern microprocessor. Thus, interconnect latency must be taken into account as a new design parameter in future synthesis and optimization tools at the architectural, as well as synthesis, level. To this purpose, this paper proposes a new latency-aware technique for the performance-driven concurrent insertion of flip-flops and repeaters in very large scale integration circuits, also taking clock skew into account. Pipelined interconnects are optimally designed for minimum latency or to meet latency constraints at the receivers. Given its generality, our methodology can be used to extend many existing techniques to the broader case of pipelined interconnects. An experimental scaling study showing overwhelming evidence of an exponential increase in the number of clocked repeaters every process generation, for high-performance microprocessors, as well as high-end application specific integrated circuits, is also presented. Such an increase indicates a radical change in current design methodologies to cope with this new emerging problem.