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Scheduling analysis integration for heterogeneous multiprocessor SoC

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3 Author(s)
K. Richter ; Inst. of Comput. & Commun. Network Eng., Tech. Univ. of Braunschweig, Germany ; R. Racu ; R. Ernst

Today, only very few techniques out of the host of work on formal performance and timing analysis have been adopted in MpSoC (multiprocessor system-on-chip) design. One of the key reasons is a mismatch between the scheduling models assumed in most formal approaches and the heterogeneous world of MpSoC scheduling techniques and communication patterns. This heterogeneity results from IP reuse and a plug-and-play design style, required to effectively reach the necessary design productivity. A second problem is the model complexity. While complex, specialized models can find their way into industry niches, their broad acceptance is extremely doubtful. In this paper, we review the existing scheduling analysis techniques with respect to these key requirements and derive a good compromise between model simplicity on the one hand, and applicability to MpSoC design on the other hand. The approach represents system-level scheduling analysis as a flow-analysis problem for event streams that can be configured to reuse the existing local scheduling analysis techniques. We define transformations between few key event stream models to meet the interfacing requirements of the compositional design style. An example demonstrates the application of the approach, as well as the worthiness of the results.

Published in:

Real-Time Systems Symposium, 2003. RTSS 2003. 24th IEEE

Date of Conference:

3-5 Dec. 2003