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Design methodology for high performance heterogeneous SoC's for converged metropolitan area networks

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3 Author(s)
Gopi, P. ; Marvell Semicond. Inc., Irvine, CA, USA ; Chao, E. ; Li, G.P.

We present a top-down design methodology for scalable multi-gigabit per second packet networking silicon in standard CMOS processes. The theory is used to drive the design of a 2.5-10 Gbps packet forwarding SoC with deterministic latency for high performance voice gateways.

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VLSI Technology, Systems, and Applications, 2003 International Symposium on

Date of Conference: