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A 1.2V low leakage low cost 90 nm CMOS wireless technology with a 60 nm transistor gate length

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18 Author(s)
Yang, S. ; Texas Instrum., Dallas, TX, USA ; Pollack, G. ; Wang, X. ; Potla, S.
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In this paper, we have demonstrated a low-leakage low-cost 90 nm technology with a 60 nm gate length for high performance operation by using 193 nm strong-phase-shift lithography, nitrided gate oxide, aggressively scaled MDD junctions and 6-level Cu/low-k interconnects.

Published in:

VLSI Technology, Systems, and Applications, 2003 International Symposium on

Date of Conference:

6-8 Oct. 2003

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