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Novel techniques for scaling deep trench DRAM capacitor technology to 0.11 μm and beyond

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12 Author(s)
P. S. Parkinson ; IBM Semicond. Res. & Dev. Center, Hopewell Junction, NY, USA ; K. Settlemyer ; I. McStay ; D. -G. Park
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In this paper we discuss the use of area enhancement techniques to increase capacitance while minimizing node leakage in 0.11 μm deep trench capacitors. The thinning of conventional SiN/SiO2 dielectric is discussed and its effectiveness for future generations assessed. Other capacitance enhancement schemes examined rely on independently enhancing the capacitor surface area while retaining the critical dimensions of the trench top with a protective SiN film. Area enhancement schemes reviewed include bottling of non-rotated and rotated wafers-(100) notch-aligned, and hemispherical-grained silicon deposition. We have demonstrated these capacitance enhancement techniques on 0.11 μm ground rules, and have achieved more than 55% capacitance enhancement while still maintaining less than 1 fA/cell leakage. We also report reliable operational lifetimes on capacitance enhanced structures. The scalability of these area enhancement techniques is examined.

Published in:

VLSI Technology, Systems, and Applications, 2003 International Symposium on

Date of Conference:

6-8 Oct. 2003