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A comparison of BDDs, BMC, and sequential SAT for model checking

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4 Author(s)
G. Parthasarathy ; California Univ., Santa Barbara, CA, USA ; M. K. Iyer ; K. -T. Cheng ; L. C. Wang

BDD-based model checking and bounded model checking (BMC) are the main techniques currently used in formal verification. In general, there are robustness issues in SAT-based versus BDD-based model checking. The research reported in this paper attempts to analyze the asymptotic run-time behavior of modern BDD-based and SAT based techniques for model checking to determine the circuit characteristics which lead to worst-case behavior in these approaches. We show evidence for a run-time characterization based on sequential correlation and clause density. We demonstrate that it is possible to predict the worst-case behavior of BMC based on these characterizations. This leads to some interesting insights into the behavior of these techniques on a variety of example circuits.

Published in:

High-Level Design Validation and Test Workshop, 2003. Eighth IEEE International

Date of Conference:

12-14 Nov. 2003