By Topic

A 80-Gbit/s D-type flip-flop circuit using InP HEMT technology

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Suzuki, T. ; Fujitsu Labs. Ltd., Atsugi, Japan ; Takahashi, T. ; Hirose, T. ; Takigawa, M.

80 Gbit/s operation of a static D-type flip-flop (D-FF) circuit was achieved using InP-based HEMT technology with a cut-off frequency of 245 GHz and a transconductance of 1500 mS/mm. To generate 80 GHz differential clock signals from the single phase one in the circuit, a rat-race circuit was placed in front of the clock buffer. The power supply voltage was -5.7 V and power consumption was 1.2 W. Its performance was measured using a selector module that we developed. The results showed that the D-FF operated at 80 Gbit/s, which was more than half as much again as speeds reported to date.

Published in:

Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 2003. 25th Annual Technical Digest 2003. IEEE

Date of Conference:

9-12 Nov. 2003