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6-bit 500 MHz flash A/D converter with new design techniques

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2 Author(s)

The authors present a 6-bit 500 Msample/s CMOS flash analogue-to-digital converter (ADC) with new design techniques. A technique referred to as the new autozeroing with interpolation (NAI) technique is proposed to include both autozeroing without idle time and interpolation operations at the same time in this high-speed low-latency flash ADC. A switching preamplifier is used in NAI to avoid using non-overlapped control signals required by conventional autozeroing ADCs and to eliminate the interference, caused by the high-speed autozeroing operation, at input nodes. Also, NAI has the benefit of a single-phase control to avoid synchronisation problems since multiphase clock signals are necessary for flash ADCs with autozeroing. While charge injection and feedthrough in NAI limit the ADC performance, a capacitor averaging technique is incorporated with NAI to decrease these errors. A negative impedance compensation technique is used to overcome the speed limitation of interpolation operations so that the ADC can operate at a high sampling rate. The designed ADC is fabricated in 0.25 μm 1P5M CMOS technology and occupies an active area of 0.3 mm2. The measurement results show that the design can achieve a sampling rate of 500 MHz with a SNR>30 dB. The total chip draws 261 mW from a 2.5 V power supply

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Circuits, Devices and Systems, IEE Proceedings -  (Volume:150 ,  Issue: 5 )