By Topic

CMOS 2.4 GHz receiver front end with area-efficient inductors and digitally calibrated 90° delay network

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $33
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
C. -H. Wu ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; C. -C. Tang ; K. -H. Li ; S. -I. Liu

A 2.4 GHz CMOS Hartley image-reject receiver utilising the area-efficient inductors and a digitally calibrated 90° delay network is proposed. Compared with the conventional planar inductor, the proposed area-efficient inductor saves 80% of the silicon area without degrading the quality factor. In addition, employing the digitally calibrated 90° delay network rather than the RC-CR network can make the traditional Hartley receiver tolerant to temperature and process variations. A prototype chip with a fully integrated low-noise amplifier followed by the proposed image-reject mixer has been fabricated in a 0.35 μm single-poly-four-metal standard CMOS technology and the active area is 3.13 mm2. While operating at 2.4 GHz, this receiver achieves a 30 dB image-rejection ratio, a -3 dB third-order input intermodulation intercept point, and an 11 dB noise figure with 54 mW power consumption from a 3.3 V supply

Published in:

IEE Proceedings - Circuits, Devices and Systems  (Volume:150 ,  Issue: 5 )