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CMOS 2.4 GHz receiver front end with area-efficient inductors and digitally calibrated 90° delay network

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4 Author(s)
Wu, C.-H. ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Tang, C.-C. ; Li, K.-H. ; Liu, S.-I.

A 2.4 GHz CMOS Hartley image-reject receiver utilising the area-efficient inductors and a digitally calibrated 90° delay network is proposed. Compared with the conventional planar inductor, the proposed area-efficient inductor saves 80% of the silicon area without degrading the quality factor. In addition, employing the digitally calibrated 90° delay network rather than the RC-CR network can make the traditional Hartley receiver tolerant to temperature and process variations. A prototype chip with a fully integrated low-noise amplifier followed by the proposed image-reject mixer has been fabricated in a 0.35 μm single-poly-four-metal standard CMOS technology and the active area is 3.13 mm2. While operating at 2.4 GHz, this receiver achieves a 30 dB image-rejection ratio, a -3 dB third-order input intermodulation intercept point, and an 11 dB noise figure with 54 mW power consumption from a 3.3 V supply

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Circuits, Devices and Systems, IEE Proceedings -  (Volume:150 ,  Issue: 5 )