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A new FRAM (ferroelectric RAM) design method, utilising a bit-plate parallel cell architecture is presented. This method is effective in reducing circuit and layout overhead caused by the on-pitch plate control circuitry. It also reduces the power consumption in the memory array. Implementation results for a 0.13 μm CMOS technology, 512 kb FRAM prototype show that the memory block area in the proposed architecture is 15.6% less than that of a conventional structure.