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Partitioning algorithms for layout synthesis from register-transfer netlists

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2 Author(s)
Wu, A.C.H. ; Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA ; Gajski, D.D.

A partitioning methodology that exploits the regularity of register-transfer components is presented, and partitioning algorithms that are used to generate the floor plan are described. The partitioning algorithms not only select the layout style best suited for each component, but also consider critical paths, I/O pin locations, and connections between components. This approach improves the overall area utilization and minimizes the wire length on the critical paths

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:11 ,  Issue: 4 )