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Equivalence checking using independent cuts [logic design verification]

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4 Author(s)
Zhan Xu ; Inst. of VLSI Design, Zhejiang Univ., Hangzhou, China ; Xiaolang Yan ; Yongjiang Lu ; Haitong Ge

With the increase in the complexity of present day systems, proving the correctness of a design has become a major concern. This paper describes a novel implementation of a BDD-based combinational equivalence checking (CEC) tool, which is distinguished from others by one heuristic. It is proposed to select an effective cut, with no dependence remaining. In addition, successfully verification of all the ISCAS'85 benchmark circuits demonstrates the efficiency of our approach.

Published in:

Test Symposium, 2003. ATS 2003. 12th Asian

Date of Conference:

16-19 Nov. 2003