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We explore an approach to input test data compression called realignment. Realignment changes a test sequence T consisting of n-bit vectors into a sequence T(m) consisting of m-bit vectors for m ≥ n. It then compresses T(m) instead of T to achieve larger levels of compression for T(m) than for T. By controlling m, realignment provides a range of possible solutions that differ in the data volume reduction and the amount of memory required between the decompressor and the circuit. The memory is required in order to translate m-bit vectors produced by the decompressor into n-bit vectors required by the circuit. We present experimental results to demonstrate this tradeoff for synchronous sequential circuits.