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A DFT selection method for reducing test application time of system-on-chips

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5 Author(s)
Miyazaki, M. ; Design Technol. Dev. Dept., Semicond. Technol. Acad. Res. Center, Yokohama, Japan ; Hosokawa, T. ; Date, H. ; Muraoka, M.
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This paper proposes an SoC test architecture generation framework. It contains a database which stores the test cost information on several DFTs for every core, and DFT selection part which performs DFT selection for test cost minimization using this database in the early phase of the design flow. Moreover, the DFT selection problem is formulated and the algorithm which solves it is proposed Experimental results showed that bottlenecks in test application time when using the single DFT method for all cores in a SoC are reduced by performing DFT selection from several DFTs. As a result, the whole test application time is drastically shortened.

Published in:

Test Symposium, 2003. ATS 2003. 12th Asian

Date of Conference:

16-19 Nov. 2003