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Power conscious BIST design for sequential circuits using ghost-FSM

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2 Author(s)
S. Roy ; Dept. of Comput. Sci. & Eng., Kalyani Govt. Eng. Coll., India ; B. K. Sikdar

This paper presents an efficient BIST scheme with low power consumption for sequential circuits. The BIST structure is obtained by using a ghost-FSM. A multiobjective genetic algorithm (MOGA) is employed to optimize the twin criteria of BIST quality and power consumption of the resultant circuit simultaneously. The scheme ensures enhancement of fault coverage along with minimization of power overhead of the BISTed circuits. Experimental results on MCNC benchmarks confirm the effectiveness of the proposed scheme to produce circuits with improved fault efficiency along with lower power consumption.

Published in:

Test Symposium, 2003. ATS 2003. 12th Asian

Date of Conference:

16-19 Nov. 2003