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An efficient built-in self-repair approach, column-block-level reconfiguration methodology, is proposed. It is based on the concept of divided bit-line (DBL) for high-capacity memories including SRAMs and DRAMs, widely used in low-power memory designs. However, the inherent characteristics (two or more memory cells are combined together to divide the bit-line into several sub bit-lines) of divided bit-line memories have not been used for fault-tolerant applications. Therefore the column block repair (CBR) fault-tolerant architecture is proposed based on the structure of DBL for high-capacity memories. The redundant columns of a memory array are divided into column blocks and reconfiguration is performed at the column block level instead of the traditional column level. The fault-tolerant architecture can improve the yield for memory fabrication significantly. Moreover, the characteristics of low power and fast access time of DBL memories are also preserved. The reconfiguration mechanism of the CBR architecture requires negligible hardware overhead. According to experimental results, the hardware overheads are less than 0.58% and 0.012% for 256-Kbit SRAMs and 8-Mbit DRAMs, respectively. The repair rate of the approach is compared with previous memory repair algorithms. It is found that the CBR approach improves the repair rate significantly. The yield improvement over traditional column-based approaches is also analysed. Simulated results show that the present approach can significantly improve fabrication yield.