Cart (Loading....) | Create Account
Close category search window

Interactive built-in self-test compression for testing a system-on-a-chip

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Kay, D. ; Cisco Systems, San Jose, CA, USA ; Mourad, S.

A methodology for test data compression and decompression in an interactive built-in self-test (iBIST) environment is presented. This methodology not only takes advantage of the strength of BIST in compression and test execution, but also overcomes BIST weaknesses by making it externally controllable. The data compression technique is realised in two steps. The first step consists of developing data to control the linear feedback self-register in generating patterns for random pattern resistant faults only. The second step uses a loss-less code to encode the control data and employs a loss-less and low-cost on-chip decodable coding scheme. A particular code was developed to illustrate the methodology; however, other codes may also be used within this environment. The proposed iBIST environment is well suited for compressing test data for the embedded logic cores in a system-on-a-chip. However, it can as well be used for component level testing. The experimental results obtained suggest that this compression scheme is comparable to the best technique available in the present literature. Furthermore, the decoding logic is estimated to be very low, e.g. less than 0.1% for cores of sizes of 100K gates or more. The architecture of test execution and its control including the decoding logic for the iBIST environment are also presented. The on- or off-chip first-in, first-out aspect of the architecture can ease the tight constraints of running a decoder synchronous to the external tester clock frequency.

Published in:

Computers and Digital Techniques, IEE Proceedings -  (Volume:150 ,  Issue: 4 )

Date of Publication:

18 July 2003

Need Help?

IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.