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A robust and scalable technique for the constraints solving problem in high-level verification

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1 Author(s)
Iyer, M.A. ; Synopsys Inc., Mountain View, CA, USA

Constraints solving is an important problem in a random simulation-based functional verification methodology. Constraints are used to model the environmental restrictions of the design under verification and the job of the constraints solver is to produce multiple random solutions that satisfy the constraints. We present RACE, a new word-level ATPG-based system for solving combinational constraint expressions. RACE builds a high-level circuit model to represent the constraints and implements a branch-and-bound algorithm to solve them. Experimental results on industrial test cases demonstrate the effectiveness of RACE. RACE has been successfully used for random stimulus generation in the context of a commercial high-level test-bench automation tool with simulation for RTL verification.

Published in:

Microprocessor Test and Verification: Common Challenges and Solutions, 2003. Proceedings. 4th International Workshop on

Date of Conference:

29-30 May 2003