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Embedded compact deterministic test for IP-protected cores

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3 Author(s)
Kinsman, A.B. ; Dept. of Electr. & Comput. Eng., McMaster Univ., Hamilton, Ont., Canada ; Hewitt, J.I. ; Nicolici, N.

Motivated by the difficulty of implementing pseudo-random built-in self-test (BIST) to non-BIST-ready intellectual properly (IP) cores, this paper introduces StreamBIST, a new low cost methodology for embedded deterministic test. By combining low overhead pseudo-random on-chip generation with external control for test pattern expansion, the proposed StreamBIST methodology provides maximum coverage for IP core compact and deterministic test sets. In addition to guaranteeing IP-protection, StreamBIST facilitates reduction in volume of test data, testing time, tester channel capacity requirements and it can seamlessly be integrated into the existing tool flows for modular system-on-a-chip (SOC) testing.

Published in:

Defect and Fault Tolerance in VLSI Systems, 2003. Proceedings. 18th IEEE International Symposium on

Date of Conference:

3-5 Nov. 2003