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Chip level power supply partitioning for IDDQ testing using built-in current sensors

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2 Author(s)
Prasad, A. ; Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA ; Walker, D.M.H.

The International Technology Roadmap for Semiconductors projects that IDDQ levels will rise rapidly with each technology node. In addition, manufacturing variations in the IDDQ level will be difficult to control. This combination will make it increasingly difficult to distinguish defect-free from defective chips via IDDQ tests. Built-in current sensors (BICSs) have been proposed to increase test resolution by virtually partitioning the supply mesh, so that each partition has a relatively small defect-free IDDQ level. In the future, such a scheme would require 100000 or more BICSs and thus the partitioning task needs to be automated. This paper presents a practical methodology to carry out this power supply partitioning.

Published in:

Defect and Fault Tolerance in VLSI Systems, 2003. Proceedings. 18th IEEE International Symposium on

Date of Conference:

3-5 Nov. 2003