By Topic

A high-speed and low-voltage associative co-processor with Hamming distance ordering using word-parallel and hierarchical search architecture

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Oike, Y. ; Dept. of Electron. Eng., Univ. of Tokyo, Japan ; Ikeda, M. ; Asada, K.

We present a new concept and its circuit implementation for a high-speed and low-voltage associative co-processor with Hamming distance ordering. A hierarchical search architecture keeps high speed in large input number. Our circuit implementation allows unlimited data base capacity and achieves low-voltage operation under 1.0 V for SoC applications, which are difficult for the conventional analog approaches. The search logic embedded in a memory cell realizes word-parallel Hamming distance ordering for high-speed sorting/routing applications as well as near/nearest-match detection for recognition. Our fabricated 0.18 μm 64-bit 32-word associative co-processor operates at 411.5 MHz and 40.0 MHz at 1.8 V and 0.75 V respectively.

Published in:

Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003

Date of Conference:

21-24 Sept. 2003