A 12-bit 20-MS/s pipelined ADC with nested digital background calibration

A 12-b 20-MS/s pipelined ADC is calibrated using an algorithmic ADC, which is itself calibrated. With background calibration, the peak SNDR and SFDR of the pipeline are 70.8 dB and 93.3 dB, respectively. The total power dissipation is 254 mW from 3.3 V. The active area is 7.5 mm/sup 2/ in 0.35 /spl mu/m CMOS.