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Resistance ratio read (R3) architecture for a burst operated 1.5V MRAM macro

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5 Author(s)
Inaba, T. ; SoC Res. & Dev. Center, Toshiba Corp., Yokohama, Japan ; Tsuchida, K. ; Sugibayashi, T. ; Tahara, S.
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A novel resistance ratio read (R3) architecture for a magnetoresistive random access memory (MRAM), which realizes a burst read operation and higher fluctuation immunity of MTJ resistance, is proposed. In this architecture, a memory cell consists of 2 transistors and 2 MTJs, which store the complementary data, and the intermediate node between these MTJs is connected to a sense amplifier. The readout signal is proportional to the ratio of 2 MTJ resistances. The proposed R3 architecture provides a simple read system which enables the introduction of a burst read mode. This architecture has a higher fluctuation immunity of MTJ resistance compared with the conventional current signal read scheme. Moreover, the proposed architecture can easily modify the macro specification to satisfy the demands of the customer, because the burst length and random access time are adjustable by the dimensions of the memory cell array.

Published in:

Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003

Date of Conference:

21-24 Sept. 2003