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Pipelined match-lines and hierarchical search-lines for low-power content-addressable memories

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2 Author(s)
Pagiamtzis, K. ; Dept. of Electr. & Comput. Eng., Univ. of Toronto, Ont., Canada ; Sheikholeslami, A.

This paper presents a pipelined match-line and a hierarchical search-line architecture to reduce power in content-addressable memories (CAM). The overall power reduction is 60%, with 29% contributed by the pipelined match-lines and 31% contributed by the hierarchical search-lines. This proposed architecture is employed in the design of a 1024×144 bit ternary CAM, achieving 7 ns search cycle time at 2.89 fJ/bit/search in a 0.18 μm CMOS process.

Published in:

Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003

Date of Conference:

21-24 Sept. 2003