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A 10-Gb/s CMOS clock and data recovery circuit using a secondary delay-locked loop

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8 Author(s)
Woogeun Rhee ; T. J. Watson Res. Center, Yorktown Heights, NY, USA ; Ainspan, H. ; Rylov, S. ; Rylyakov, A.
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A 10 Gb/s clock and data recovery (CDR) circuit and a 1:4 DMUX are implemented in 0.12 μm CMOS. The CDR employs a secondary wideband delay-locked loop (DLL) to enable independent bandwidth control for jitter transfer and jitter tolerance. The proposed clock recovery and data recovery (CRDR) system enhances the jitter tolerance at high frequencies and offers less data-pattern-dependency for CDRs that use a binary phase detector.

Published in:

Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003

Date of Conference:

21-24 Sept. 2003