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Real-time L3 cache simulations using the Programmable Hardware-Assisted Cache Emulator (PHA$E)

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7 Author(s)
Chalainanont, N. ; Sch. of EECS, Oregon State Univ., Corvallis, OR, USA ; Nurvitadhi, E. ; Morrison, R. ; Lixin Su
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As the gap between the CPU and memory speeds increases, there has been an increasingly important need to study the memory-hierarchy designs. Investigations of memory performance have typically been conducted using trace-driven simulation, which could take tremendous resources (e.g. long simulation time, large storage requirements for traces, and high overall cost). Recent works have proposed the use of hardware for performing cache simulations. Such approach is advantageous as it can be done in real-time, which eliminates the need or large storage for traces, reduces the simulation time, and improves the accuracy of the results. This paper discusses our preliminary work with theProgrammable Hardware-Assisted Cache Emulator (PHA$E), a system for emulating cache in real-time. We discuss the design and implementation of our system. Furthermore, the results of simulating varying sizes of off-chip L3 caches on various workloads (SPECcpu2000, SPECjbb2000, SPECjAppServer2002, and a large vocabulary continuous speech recognition system are presented and analyzed. Lastly, future research directions are elaborated on.

Published in:

Workload Characterization, 2003. WWC-6. 2003 IEEE International Workshop on

Date of Conference:

27 Oct. 2003

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