By Topic

A version of the Byte Radix Sort algorithm suitable for the implementation in hardware

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Sonc, D. ; Ljubljana Univ., Slovenia

A version of the Byte Radix Sort (BRS) algorithm, which is suitable for the implementation in hardware, is presented. It is shown that hardware implementation eliminates most inefficiencies of the software implementation and is a candidate for the fastest known sorting technique. It is estimated that on the average more than ten-fold speed-up is possible with the hardware implementation. A penalty for greater speed is the addition of a new chip to the computer system.

Published in:

EUROCON 2003. Computer as a Tool. The IEEE Region 8  (Volume:2 )

Date of Conference:

22-24 Sept. 2003