A version of the Byte Radix Sort algorithm suitable for the implementation in hardware

A version of the Byte Radix Sort (BRS) algorithm, which is suitable for the implementation in hardware, is presented. It is shown that hardware implementation eliminates most inefficiencies of the software implementation and is a candidate for the fastest known sorting technique. It is estimated that on the average more than ten-fold speed-up is possible with the hardware implementation. A penalty for greater speed is the addition of a new chip to the computer system.