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Deterministic test generation for digital circuits by cellular automata in a Java applet

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3 Author(s)
Pikula, T. ; Inst. of Informatics, Slovak Acad. of Sci., Bratislava, Slovakia ; Gramatova, E. ; Fischerova, M.

The paper presents implementation of a test pattern generation algorithm that uses cellular automata with bit flipping to generate a pre-computed test set. The algorithm is realized as a Java applet for automatic synthesis of the built-in self-test structure into a digital circuit modeled in VHDL using only its VHDL entity. This software tool is available on the Internet.

Published in:

EUROCON 2003. Computer as a Tool. The IEEE Region 8  (Volume:2 )

Date of Conference:

22-24 Sept. 2003