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An automated design flow for optimized implementation of real-time image processing applications onto FPGA

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3 Author(s)
Kaouane, L. ; Groupe ESIEE, Noisy-Le-Grand, France ; Akil, M. ; Sorel, Y.

As the size and complexity of high performance, signal, image and control processing algorithms is increasing continuously, the implementations cost is becoming an important factor. This paper addresses this issue and presents an efficient rapid prototyping methodology to implement such high performance algorithms using reconfigurable hardware. Such reconfigurable architectures, like FPGAs, provide all the benefits of hardware acceleration while retaining the flexibility of programming. The proposed design methodology follows a seamless design flow of graph transformations from the specification to the final implementation, which is supported by SynDEx, a system level CAD software tool.

Published in:

EUROCON 2003. Computer as a Tool. The IEEE Region 8  (Volume:1 )

Date of Conference:

22-24 Sept. 2003