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Design of VLSI switch for highly parallel multiprocessor system

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4 Author(s)
Y. Hsu ; IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA ; C. Benveniste ; J. Ruedinger ; C. J. Tan

The design of a large, multistage interconnection network that has been successfully constructed and used in a version of the RP3 system is described. The network hardware is scalable and can be used for systems consisting of anywhere from four to hundreds of processor and memory elements. An overview is given of the switch architecture, followed by the packaging structure. A description of the methodology used for logic design and verification of the large silicon chip is presented

Published in:

Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990

Date of Conference:

13-16 May 1990