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Effect of device and interconnect scaling on the performance and noise of packaged CMOS devices

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2 Author(s)
R. Senthinathan ; Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA ; J. L. Prince

A detailed investigation of the effects of device and interconnect scaling on CMOS performance and noise was performed for multilayer packages. Results of simulations using experimental scaled-device data for one micron and two micron Leff, and recently developed modeling tools for interconnect parasitics, were obtained. These results were compared to predicted performance and noise characteristics obtained using conventional constant-voltage scaling schemes. Significant differences were found

Published in:

Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990

Date of Conference:

13-16 May 1990