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Methodology for on-chip adaptive jitter minimization in phase-locked loops

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3 Author(s)
Mansuri, M. ; Dept. of Electr. Eng., Univ. of California, Los Angeles, CA, USA ; Hadiashar, A. ; Yang, C.-K.K.

This paper describes a run-time adaptive method of minimizing jitter for a phase-locked loop (PLL). The design employs digital tuning that independently adjusts each loop parameter of the PLL. The loop is fabricated in 0.25 μm CMOS and uses a 2.5 V supply. The proposed method measures the output jitter on-chip and adjusts the PLL loop parameters toward minimizing the jitter by a closed-loop control system. The experimental results verify the success of the proposed method in minimizing jitter to within 5 ps of the minimum peak-to-peak jitter.

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Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on  (Volume:50 ,  Issue: 11 )