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Techniques for in-band phase noise reduction in ΔΣ synthesizers

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4 Author(s)

This paper reviews several techniques used to reduce the in-band phase noise contribution of ΔΣ fractional-N frequency synthesizers. The paper develops several practical techniques for specifying the noise and linearity of components used in a ΔΣ fractional-N synthesizer. As an example, it presents a synthesizer with an in-band phase noise floor of -97 dBc/Hz@10 KHz for an RF output frequency of 2.432 GHz and a reference frequency of 16 MHz. The synthesizer has a frequency resolution of 61 Hz and an on-chip crystal oscillator. The synthesizer was implemented in a 0.35-μm SiGe process and consumes 6 mA from a 3 V supply. The in-band phase-noise, spurs, and power consumption of this synthesizer are each low and comparable to the state of the art.

Published in:

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on  (Volume:50 ,  Issue: 11 )

Date of Publication:

Nov. 2003

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