By Topic

Design and characterization of convention self-timed multipliers

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Bandapati, S.K. ; Missouri Univ., Rolla, MO, USA ; Smith, S.C. ; Choi, M.

We present various 4-bit × 4-bit unsigned multipliers designed using the delay-insensitive convention logic (NCL) paradigm. They represent bit-serial, iterative, and fully parallel multiplication architectures. NCL is a self-timed logic paradigm in which control is inherent in each datum. NCL follows the so-called weak conditions of Seitz's delay-insensitive signaling scheme. Like other delay-insensitive logic methods, the NCL paradigm assumes that forks in wires are isochronic. NCL uses symbolic completeness of expression to achieve delay-insensitive behavior. Simulation results show a large variance in circuit performance in terms of power, area, and speed. This study serve as a good reference for designers who wish to accomplish high-performance, low-power implementations of clockless digital VLSI circuits.

Published in:

Design & Test of Computers, IEEE  (Volume:20 ,  Issue: 6 )