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New systolic architectures for inversion and division in GF(2m)

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2 Author(s)
Z. Yan ; Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA ; D. V. Sarwate

We present two systolic architectures for inversion and division in GF(2m) based on a modified extended Euclidean algorithm. Our architectures are similar to those proposed by others in that they consist of two-dimensional arrays of computing cells and control cells with only local intercell connections and have O(m2) area-time product. However, in comparison to similar architectures, both our architectures have critical path delays that are smaller, gate counts that range from being considerably smaller to only slightly larger, and latencies that are identical for inversion but somewhat larger for division. One architecture uses an adder or an (m+l)-bit ring counter inside each control cell, while the other architecture distributes the ring counters into the computing cells, thereby reducing each control cell to just two gates.

Published in:

IEEE Transactions on Computers  (Volume:52 ,  Issue: 11 )