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CMOS VLSI implementation of a low-power logarithmic converter

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2 Author(s)
K. H. Abed ; Dept. of Electr. Eng., Wright State Univ., Dayton, OH, USA ; R. E. Siferd

We present a unique 32-bit binary-to-binary logarithm converter including its CMOS VLSI implementation. The converter is implemented using combinational logic only and it calculates a logarithm approximation in a single clock cycle. Unlike other complex logarithm correcting algorithms, three unique algorithms are developed and implemented with low-power and fast circuits that reduce the maximum percent errors that result from binary-to-binary logarithm conversion to 0.9299 percent, 0.4314 percent, and 0.1538 percent. Fast 4, 16, and 32-bit leading-one detector circuits are designed to obtain the leading-one position of an input binary word. A 32-word×5-bit MOS ROM is used to provide 5-bit integers based on the corresponding leading-one position. Both converter area and speed have been considered in the design approach, resulting in the use of a very efficient 32-bit logarithmic shifter in the 32-bit logarithmic converter. The converter is implemented using 0.6μm CMOS technology, and it requires 1,600λ×2,800λ of chip area. Simulations of the CMOS design for the 32-bit logarithmic converter, operating at VDD equal to 5 volts, run at 55 MHz, and the converter consumes 20 milliwatts.

Published in:

IEEE Transactions on Computers  (Volume:52 ,  Issue: 11 )