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Modulo 2n±1 adder design using select-prefix blocks

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3 Author(s)
Efstathiou, C. ; Dept. of Informatics, TEI, Athens, Greece ; Vergos, H.T. ; Nikolos, D.

We present new design methods for modulo 2n±1 adders. We use the same select-prefix addition block for both modulo 2n-1 and diminished-one modulo 2n+1 adder design. VLSI implementations of the proposed adders in static CMOS show that they achieve an attractive combination of speed and area costs.

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Computers, IEEE Transactions on  (Volume:52 ,  Issue: 11 )