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Optimized synthesis techniques for testable sequential circuits

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2 Author(s)
B. Eschermann ; Inst. fuer Rechnerentwurf und Fehlertoleranz, Karslruhe Univ., Germany ; H. -J. Wunderlich

The authors describe a synthesis approach that maps a behavioral finite state machine (FSM) description into a testable gate-level structure. The term testable, besides implying the existence of tests, also means that the application of test patterns is facilitated. Depending on the test strategy, the state registers of the FSM are modified, e.g. as scan path or self-test registers. The additional functionality of these state registers is utilized in system mode by interpreting them as smart state registers, capable of producing certain state transitions on their own. To make the best use of such registers, the authors propose a novel state encoding strategy based on an analytic formulation of the coding constraint satisfaction problem as a quadratic assignment problem. An additional minimization potential can be exploited by appropriately choosing the pattern generator for self-testable designs. Experimental results indicate that, compared with conventional design for testability approaches, significant savings are possible this way

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:11 ,  Issue: 3 )