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Synthesis of robust delay-fault-testable circuits: practice

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2 Author(s)
Devadas, S. ; Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA ; Keutzer, K.

The authors show how an orchestration of combinational synthesis for testability approaches can result in logic-level implementations of large integrated circuit designs that are completely robustly gate-delay-fault and path-delay-fault testable. For control portions of VLSI circuits, Boolean covering and algebraic factorization procedures that guarantee path-delay-fault testability are used, starting from a sum-of-products representation of a function. Hierarchical composition rules are used in the synthesis of regular structures occurring in data path portions, such as parity generators and arithmetic units. It is shown how test vectors to detect all path delay faults can be obtained as a by-product of the synthesis process. These techniques were used on circuits with over 5000 gates, and preliminary experimental results on a data encryption chip, a small microprocessor, and a speech recognition chip are presented

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:11 ,  Issue: 3 )