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Test compaction for sequential circuits

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4 Author(s)
Niermann, T.M. ; Sunrise Test Syst., Los Altos, CA, USA ; Roy, R.K. ; Patel, J.H. ; Abraham, J.A.

The authors describe a number of heuristic algorithms to compact a set of test sequences generated by a sequential circuit automatic test pattern generator (ATPG). A model has been developed and analyzed which shows that finding the optimal solution has an exponential worst-case complexity. To achieve an acceptable run time, some heuristics have been developed that yield good suboptimal solutions in a very short time. Three heuristic algorithms were developed. These algorithms were implemented in C and lex and applied to several of the ISCAS-89 benchmark sequential circuits. They reduce the test length by 17%-63% with a very small time overhead, while having little effect on the original fault overage

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:11 ,  Issue: 2 )