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Modeling of nMOS transistors for simulation of hot-carrier-induced device and circuit degradation

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2 Author(s)
Leblebici, Y. ; Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA ; Sung-Mo Kang

The authors present an accurate one-dimensional device model for the simulation of nMOS transistors with hot-carrier-induced oxide damage. The model uses a realistic charge density distribution profile to account for the localization of the oxide-interface charge near the drain. Model simulation results obtained for nMOS transistors with hot-carrier-induced oxide damage demonstrate good agreement with the experimental data. The amount and the location of the hot-carrier-induced oxide damage are simulated by using only a few parameters, which simplifies the implementation of the model in a reliability simulation environment. The proposed model has been implemented in the iSMILE circuit simulator, and the capabilities of the model have been explored by various circuit simulation examples. The damaged-MOSFET model presented offers a simple and accurate approach for simulating the circuit behavior after hot-carrier damage

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:11 ,  Issue: 2 )