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PROOFS: a fast, memory-efficient sequential circuit fault simulator

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3 Author(s)
Niermann, T.M. ; Sunrise Test Syst., Sunnyvale, CA, USA ; Wu-Tung Cheng ; Patel, J.H.

The authors describe PROOFS, a fast fault simulator for synchronous sequential circuits, PROOFS achieves high performance by combining all the advantages of differential fault simulation, single fault propagation, and parallel fault simulation, while minimizing their individual disadvantages. The fault simulator minimizes the memory requirements, reduces the number of gate evaluations, and simplifies the complexity of the software implementation. PROOFS requires an average of one fifth the memory required for concurrent fault simulation and runs six to 67 times faster on the ISCAS-89 sequential benchmark circuits

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:11 ,  Issue: 2 )

Date of Publication:

Feb 1992

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